1. Field of the Invention
The present invention relates to a method of manufacturing a variable capacitance diode and the variable capacitance diode, more particularly to the variable capacitance diode, which is provided with MOS (metal oxide semiconductor) or a bipolar transistor and made into an integrated circuit.
2. Description of the Related Art
Along with the downsizing of mobile communication devices such as a portable telephone, one-chip technology has been promoted for circuits including external parts, such as a frequency synthesizer (PLL) and a voltage control oscillator. A variable capacitance diode constituting the VCO on a semiconductor substrate serves to control a capacitance value through the application of a reverse bias voltage utilizing a depletion-layer capacitance of pn-junction. It is necessary to integrate the variable capacitance diode so as to have a large capacitance variation ratio relative to a variation of the given voltage.
Referring to reference numerals in FIG. 10 illustrating an example of a conventional variable capacitance diode, 41 denotes an n type semiconductor substrate, 42 denotes an n− region, 43 denotes an n region, 44 denotes an n′ region, 45 denotes a cathode layer, 46 denotes a pn-junction, 47 denotes an anode layer (p+ region) and 48 denotes an inter-layer insulation film. The reverse bias voltage is applied to the pn-junction 46 so as to constitute the variation capacitance diode by means of a depletion layer mainly spreading in the cathode layer 45. FIG. 11 is a graph showing a distribution of an impurity concentration in section taken along D-D line of FIG. 10.
As a structure-wise demand to keep up with the miniaturization of a circuit element, the anode layer 47 is necessarily formed in a size larger than the cathode layer 45. In the case of the variable capacitance diode having the large capacitance variation ratio, a concentration gradient in the n′ region of the pn junction portion is steep. Therefore, a concentration variation in connection with a fluctuation in the manufacturing process tends to be large. As a result, the variable capacitance ratio results in a significant fluctuation.
A key factor in obtaining the large capacitance variation ratio is to optimize a surface impurity concentration in a region where the pn-junction is formed and an impurity concentration profile and the like.
Referring to reference numerals in FIG. 12 illustrating another example of the conventional variable capacitance diode, 51 denotes an n type semiconductor substrate, 52 denotes a p− region, 53 denotes a p region, 54 denotes an anode layer, 55 denotes a pn junction, 56 denotes a cathode layer (n+ region), 57 denotes an inter-layer insulation film, 58 denotes an anode contact layer, 59 denotes an anode electrode and 60 denotes a cathode electrode. The reverse bias voltage is applied to the pn-junction 55 so as to constitute the variation capacitance diode using a depletion layer mainly spreading in the anode layer 54. FIG. 13 is a graph showing a distribution of an impurity concentration in section taken along E-E line of FIG. 12. The miniaturization of the circuit element leads to the generation of a misalignment between the anode layer 54 (p region) and the cathode layer 56, which makes it difficult to improve a precision. Because a concentration gradient in the p region of the pn-junction portion is steep, the variable capacitance ratio results in a significant fluctuation.
Referring to reference numerals in FIG. 14 illustrating still another example of the conventional variable capacitance diode, 61 denotes a p type semiconductor substrate, 62 denotes an anode layer (p− type layer), 63 denotes a cathode layer (n+ type layer), 64 denotes an anode contact layer (p+ type layer) and 65 denotes a separation insulation film. Because the separation insulation film 65 is present between the n+ type layer, which is the cathode layer 63 and the p+ type layer, which is the anode contact layer 64, a capacitance component in the horizontal direction cannot be effectively utilized when the reverse bias voltage is applied. As a result, an integrated absolute capacitance value of the variable capacitance diode results in a low capacitance particularly in a low voltage range, thereby failing to obtain a sufficient capacitance variation ratio. On the contrary, it is necessary to increase an area of the variable capacitance diode in an effort to obtain a desired absolute capacitance, which makes it difficult to miniaturize the circuit element.